Wednesday, April 28, 1999
at 5:30PM

The mismatch between processor and memory speed has driven much of the complexity of modern computers, and can dominate system performance. I will describe the evolution of this mismatch for microprocessor based computers and the physics and economics that have caused it.

The memory access timing of a current commercial workstation, and the engineering tradeoffs that resulted in the design will be described in detail. The potential effects of using optical interconnects on memory timing will be examined.

Howard Davidson is a Distinguished Engineer at Sun Microsystems Laboratories. He holds a Ph.D. in Physics. His current research interests are in the interaction between the physical design and technologies used for implementing computers and the resulting limitations on the architecture and performance.

Dr. Davidson previously held positions at Lawrence Livermore National Laboratories, Schlumberger Palo Alto Research, Cray Research and Hewlett-Packard. He is chair of the 1999 IEEE Workshop on High Speed Interconnections Within Digital Systems and has chaired the IEEE System Packaging Workshop. Dr. Davidson has presented many invited papers on computer packaging and high speed interconnections. He holds 14 patents.